# TIER IV joins JST's Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving - Link: https://www.thailand-business-news.com/pr-news/tier-iv-joins-jsts-next-generation-edge-ai-semiconductor-rd-program-to-open-source-ai-chip-designs-for-autonomous-driving - Published: 2026-08-14T11:00:00+07:00 - Author: PR Newswire | | TOKYO, Aug. 14, 2026 /PRNewswire/ — [TIER IV](https://tier4.co.jp/en/), the pioneering force behind open-source software for autonomous driving, has joined the Next-Generation Edge AI Semiconductor Research and Development Program led by the Japan Science and Technology Agency (JST) to advance research and development of a software-defined system-on-chip (SoC) for Level 4 autonomous driving. Under the JST program, a research team led by Professor Yoshihiro Kawahara of Graduate School of Engineering, The University of Tokyo, will advance research into use-case-driven, functionally differentiated physical AI chip design. Meanwhile, TIER IV is developing the logic design of an AI chip designed to efficiently process inference for end-to-end (E2E) autonomous driving AI, with the goal of open-sourcing the design assets and associated toolchain. High-performance computing technologies, including graphics processing units (GPUs), have played a central role in accelerating the rapid evolution of AI. Level 4 autonomous driving, however, requires AI models to operate continuously under real-world and real-time constraints. This calls for a new approach that complements existing high- performance computing technologies while further advancing not only power efficiency, but also adaptability, transparency, and verifiability. Through this initiative, TIER IV will independently design an AI chip for autonomous driving that supports Autoware, the world’s leading open-source software for autonomous driving, and evaluate its effectiveness as part of an SoC. In addition to the chip’s logic design, TIER IV will open-source the compiler and related toolchain. By making these technologies available, TIER IV aims to establish an open ecosystem in which semiconductor manufacturers can leverage its platform technologies to accelerate the commercialization of SoCs for Level 4 autonomous driving. [⌊SoC software and hardware architecture⌉⌊SoC software and hardware architecture⌉[ SoC software and hardware architecture **Power efficiency** Autonomous driving AI increasingly relies on large-scale Transformer models that process sensor inputs, such as camera images and point cloud data, in an integrated manner from perception through motion planning. This initiative will focus on Transformer inference and develop a dedicated architecture that simplifies the complex control mechanisms required for general-purpose computing. Data required for AI model execution will be efficiently placed in advance and repeatedly reused within the chip, reducing the power consumed by external memory transfers and computation control. The architecture will also incorporate dedicated compute circuits for operations frequently used in Transformers, including matrix multiplication and attention mechanisms. Rather than optimizing only the chip’s peak performance, TIER IV will seek to improve performance per watt across the entire autonomous driving system, including Autoware. The design will support flexible deployment across a broad range of applications, from embedded devices operating at several watts to in-vehicle electronic control units operating at several tens of watts. **Adaptability** The technology landscape surrounding autonomous driving AI is evolving rapidly, making it difficult for architectures designed around a specific model or hardware configuration to adapt continuously to change. To address this challenge, TIER IV will introduce the Tensor Operator Set Architecture (TOSA), a standardized intermediate representation, between AI models and the AI chip. Operations from AI models developed in frameworks such as PyTorch will be converted into a common TOSA representation. Optimization and code generation will then be performed through TOSA before execution on the AI chip, enabling loose coupling between AI frameworks and hardware. As a result, changes in AI model architectures or computational methods can be accommodated primarily through software updates to components such as the compiler and runtime, without requiring the entire chip to be redesigned from scratch. TIER IV aims to realize a software-defined SoC whose performance and power efficiency can be continuously optimized through software. **Transparency** In safety-critical applications such as Level 4 autonomous driving, it is important to understand not only the AI model itself, but also the internal architecture and processing flow of the computing system on which it runs. Under this initiative, TIER IV will open-source the logic design of its autonomous driving AI chip, together with the compiler and related toolchain. By making the design information publicly available, TIER IV will enable semiconductor manufacturers and developers to inspect the chip’s internal architecture and software behavior, and to modify, extend, and reuse the technologies according to their vehicle platforms, AI models, performance requirements, and power constraints. Just as Autoware has enabled collaborative development of autonomous driving software, TIER IV will extend the same open-source philosophy to AI chip design and related toolchains. This will support an ecosystem in which autonomous driving AI technologies can be continuously improved and advanced without dependence on specific semiconductor products or closed development environments. **Verifiability** The process of executing an AI model on a chip involves model-format conversion, computational optimization, quantization, rounding, and other transformations. These processes are essential to improving performance and power efficiency, but they may also introduce numerical differences that affect the final computation results. A mechanism is therefore needed to assess the impact of such differences. Using TOSA and its clearly defined operator specifications as a foundation, TIER IV will structure the compilation transformation process and introduce formal verification techniques. For selected transformations and operations, the initiative will establish mechanisms to mathematically verify numerical consistency before and after transformation, as well as compliance with predefined error tolerances. Through this approach, TIER IV will pursue not only high processing performance, but also an execution environment in which the transformations applied to an AI model before chip execution can be traced and the correctness of the resulting processing can be verified. This will contribute to a more reliable execution environment for autonomous driving AI. **Supporting quotes** "Advances in AI have been accelerated by powerful computing platforms, including GPUs, which have enabled rapid progress across the industry," said **Shinpei Kato, founder and CEO of TIER IV**. "As Level 4 autonomous driving moves toward broader deployment, we believe the next step is to complement these platforms with computing architectures designed for real-world and real-time requirements. Through this initiative, we are introducing a software-defined and open approach to AI chip design that combines power efficiency, adaptability, transparency and verifiability. In particular, the ability to understand how an AI model is transformed for execution and to verify the correctness of that processing will be increasingly important as autonomous driving systems are deployed in safety-critical environments. By extending the open- source philosophy behind Autoware from software to AI chip design and related toolchains, we aim to create an open ecosystem in which automakers, semiconductor manufacturers and developers can build upon the technology and continue advancing their own systems. This represents an important step toward a scalable, adaptable and reliable computing foundation for Level 4 autonomous driving." "In physical AI applications such as robotics and autonomous driving, GPU power consumption has long been a major bottleneck for deployment on battery-powered devices," said **Professor Yoshihiro Kawahara of Graduate School of Engineering, The University of Tokyo**. "This project aims to fundamentally overcome this constraint through a functionally differentiated chip design backward-mapped from specific use cases. I look forward to TIER IV developing chips responsible for high-level decision-making– specifically, the high-level behavioral layer that handles the thinking process essential for end-to-end physical AI and autonomous driving. As the leading force behind Autoware, the global standard open-source software for autonomous driving, TIER IV is democratizing design, with an approach spanning application requirements to hardware. This enables applied researchers to shape their ideal semiconductors. This initiative, supported by an open ecosystem, has the potential to lay the foundations for a steady stream of Japanese startups creating high-value semiconductors." **About TIER IV** [TIER IV](https://tier4.co.jp/en/) stands at the forefront of deep tech innovation, pioneering [Autoware](https://github.com/autowarefoundation/autoware), open-source software for autonomous driving. With a comprehensive suite of platforms and services built around Autoware, TIER IV provides everything from software development and vehicle procurement to operational support. Through the Autoware ecosystem, TIER IV works with partners worldwide to shape the future of intelligent vehicles with open-source software, aiming to create mobility that is safer, more sustainable, and accessible to all. **Media contact[pr@tier4.jp](https://www.thailand-business-news.com/pr-news/pr@tier4.jp) The word marks and logos of TIER IV are trademarks or registered trademarks of TIER IV, Inc. in Japan and other countries. All other company names, product names, service names, and logos referenced herein are trademarks or registered trademarks of their respective owners. Autoware is a registered trademark of the Autoware Foundation. --- | This article was produced by Cision PR Newswire, our trusted news partner. The views expressed and the content presented here are solely those of the author and may not fully reflect the opinions of Thailand Business News. | --- **Read the original article :** [TIER IV joins JST's Next-Generation Edge AI Semiconductor R&D Program to open-source AI chip designs for autonomous driving ](http://www.prnasia.com/story/archive/5025795_CN25795_0?rand=184833)